Open source tools in education: tape out a chip in a semester!
Interview with UC berkeley PhD Student Nayiri Kalindjian
Q: So, I guess one of the fun questions would be,
what makes you to wake up in the morning
or to stay up in the light,
given you're a night owl, I guess.
A: I think it's these very hard problems in chip design.
Yeah, I think once you start working on it,
it's really hard to tear yourself away from it.
Because I guess the problems are so diverse
and they're so difficult to solve.
So, usually, you know, you see a design
that's not meeting timing
and there's just so many different ways
you could go about fixing it.
So, I think I just enjoy, like, how varied.
The problem is as opposed to just, like, coding
where you're kind of looking at one program
and just chasing bugs.
Like, here there's so many different things
that could have gone wrong.
So, I think I enjoy that aspect.
And I think that it's tied to, like, something physical,
something that's going to be realized, like, in real life.
So, yeah.
I think that's just very interesting.
Q: Yeah, that's cool.
So, I think, like, you're a third year student, right?
So, like, how has been, I guess, your journey so far?
Yeah, I'm a second year, so I'm curious.
A: Yeah, so I graduated into the pandemic
at the start of the pandemic.
Yeah, so all of my, like, grad school visits were,
or most of mine were canceled,
including my one to Berkeley.
So, like, I did it remotely and, yeah,
started Berkeley remotely,
which I learned the hard way that
you can't do chip design remotely, basically.
I feel like it was very difficult
and I didn't know at the time
because I was, you know, such a beginner.
Like, first year.
I even took our, like, Berkeley tape out class.
Like, the first time we actually taped out a chip
was the semester that I was taking it in.
Like, spring 21.
And I didn't even realize, like,
how much more difficult it was
because the whole class was remote.
So, I never, like, saw my classmates,
but we still managed to, like, tape out a chip together.
So, I feel like once things went in person my second year,
I just, like, started learning things,
like, exponentially faster.
So, it's kind of, like, a testament
to Latch-Up being, like, in person again.
It's so much more productive, I feel.
So, that was kind of the start of it.
And, yeah, just, like, being confused
for the first year and a half, I think.
There's so much to learn.
And I think just being around, like,
very experienced chip designers,
I think is the only way to learn.
It's just learning from other people
because it's such an evolving field
that there's no good educational resources.
And at least, like, people try.
Like, people are presenting here,
and it's gotten better.
So, I feel like I have taught myself some things.
Like, you know, someone made a good tutorial
on, like, certain aspects of chip design,
like, DRC cleaning. But it does just change so quickly,
and it just depends on what you're trying to do,
what you're trying to create.
So, I think just, yeah, I think the biggest thing
I learned in grad school was just learning
from, you know, these fifth and sixth years
and people in industry that just kind of
have been in this field for so long.
Yeah, but it's definitely been a learning curve.
Q: I mean, definitely.
I think, yeah, I've been also, like,
playing around with, like, drivers a lot,
like, in my first year,
and it's been taking so much time.
But I think, hopefully, now I'm more comfortable,
so it will take less time,
and it will be better progress.
A: Yeah, I agree.
I think it was very frustrating to see, like,
my friends who are just doing ML
or publishing papers first year,
and I'm, like, just learning how to use, like,
RTL generators and run the VLSI flow
and, like, verify it and do sign-off
and all these things.
But I think, yeah, it's a very steep learning curve,
but once you learn everything,
so it's, like, painful.
But then I think just only recently
it's become so easy for me to switch
to, like, doing the actual research
I want to do for my dissertation,
which is, like, power modeling.
And it's been much easier
because now I just will run these flows very quickly
because I, like, know all the tools
and I know who to ask if something breaks.
So it was worth the long learning curve, basically.
But it's very painful at the beginning,
and I think it's very unique in that.
And I think it's good that it's open source.
Like, it's increasingly open source
because I feel like it's impossible to learn
in isolation.
Like, I don't know how people did it,
like, 20 years ago.
But, yeah, I think it's very helpful
with all the resources that are now available.
Q: So, like, did you know that you wanted
to do chip design, like, from the first sight
or, like, who, I guess, inspired you?
Because I think a lot of people do
chip design, essentially, at Berkeley.
A: I think it was different for other people in my lab,
but for me, I came into it more from the EE side.
So in undergrad, I joined the lab that I did.
It was, like, a low-power, very extremely low-power group,
like Ben Calhoun at UVA.
And they were basically working on self-powered devices,
which is extremely, like, you know,
micro-watt, nano-watt type circuits,
mainly for biomedical applications.
And I thought it was really cool,
because I just thought, like, how impactful it would be,
like, all of these very, very powerful, like, devices
to help people just, like, with their lives.
So that's kind of, going into grad school,
it's like, oh, I want to work on something like this,
like, more analog side.
So, yeah, I applied to my group because it kind of
did a mix of analog and digital.
But then when I got to Berkeley,
I kind of realized I didn't really like analog.
I thought it was so cool.
And I liked the abstracts of all the papers,
but I didn't find it very interesting.
And that's when I, like, kind of fell in love
with computer architecture.
It's hard not to at Berkeley, too,
because they teach it so well.
So it's kind of like, I want to make the chip,
but I don't want it to just be, like,
kind of these analog circuits that don't seem very reusable.
It doesn't seem like you learn very much.
You just kind of, like, bang on the design
until you get something that's good.
So I kind of liked that digital design kind of combined.
Like, you still have to know enough about the architecture,
but you kind of deal with the physical limitations
of, like, designing a chip.
So, yeah.
I think that's how I chose it.
Basically, like, process of elimination.
Like, don't want to do analog,
don't want to do high-level CS.
So, you know, Compaq and VLSI sound like the way to go.
Q: Yeah, I guess I had a similar past, too.
Yeah, we had this, like, professor
who used the digital design,
and I was like, ah, I mean,
it is definitely cool to have all this MOSFET,
blah, blah, blah, but do I want to do it?
So, like, I think you presented here at work, right,
like a Hammer chip.
So can you, like, quickly talk about that?
A: Basically, it started because it started
before my time as a grad student,
but Berkeley was just making increasingly complex chips,
and they wanted to be able to reuse their flows
because they realized as they switched
process technologies or different CAD tools,
it was very difficult to still reuse
all of the great work and the learning
that they had done on previous chips,
you know, as they switched from, like, Intel to TSMC
or Global Foundries.
So I think that's how they started.
They kind of scoped out what they wanted
a VLSI flow tool to do,
and they created Hammer and started building on it,
and it kind of worked really great
because around this time, like, ChipYard was starting up,
which definitely, like, ChipYard
is the more well-known infrastructure.
So as ChipYard is able to spit out
these, like, really complex SOCs,
like, we're not talking, like, you know,
an adder or, like, a little digital design.
It's, like, I mean, the RISC-V core
is, like, a tiny part of the SOC
that they're generating,
so it needed, like, a very sort of flexible,
modular VLSI flow that could then, like,
be the physical backend for these SOCs.
So that's how, basically, like,
my lab wanted to tape out these complex chips.
They needed a flow that could handle the complexity,
so that's how they started.
Like, they kept designing it.
So it's basically, like, as we tape out something
and we need, like, some functionality,
we just, like, add it into Hammer.
So it kind of, like, keeps the knowledge reuse
because, for example, like, when I came in
and I just wanted to, like, start off
and just, like, implement a simple chip,
I didn't have to, like, look at the end of this manual
or, like, understand how TCL, like, worked.
It was kind of already generated for me.
Like, the older student wrote that part
and only when it would break, I would kind of go
and, like, only read about the thing that broke,
but I didn't have to, like, write it from scratch.
So I think that, yeah, it definitely helped me.
I'm very grateful that I could just, like,
use the work from, like, previous students.
Q: So, like, Chipyard is kind of a collection of those,
those, like, digital design tools, right?
That, like, I don't know, Rocket, Boom,
or all of them are kind of saved over there
so that you can build SOC easily with the templates, right?
A: Exactly.
Q: And then Hammer is kind of VLSI model in a sense
when you will, so usually when you generate
from HGL language, some gate level knowledge,
is this what you mean by the VLSI flow?
A: Yeah, it's slightly a step above that.
It takes the HDL and then goes all the way to GDS.
So, like, Chipyard handles generating Verilog
and then Hammer handles Verilog to mapped,
like, gate level Verilog and then, like, the layout.
So it's basically just, like, if someone at Berkeley
wants to tape out, they'll use, with Chipyard,
they'll use Hammer.
But if you just wanted to, like, put your Verilog
in FPGA, then you go use, like, the FPGA flow
and that's separate.
Or if you just want to simulate it,
you do something else.
But, yeah, Jerry and Abe will do a much better job
of describing Chipyard, but, yeah,
they're definitely the main developers there.
Q: I mean, you know your part, so this is, I think,
about the collaborative research about, right?
Yeah, I guess you guys have all the stuff.
I guess usually people use Yosses, right,
like, as an alternative to Hammer.
A: Oh, so, yeah, it's kind of like,
that's, like, one of the biggest misunderstandings
about Hammer.
So I guess Hammer is, like, if you just listen
to Silicon Compiler, I think he did a better job
of explaining it than I did.
Like, it's not the actual EDA tool.
It basically is, like, a better make file
for these tools.
So Hammer has a plugin for Yosses.
So Hammer will go and run Yosses.
But the difference is once someone,
so in this case, me, like, once I, like,
added the compatibility for Yosses into Hammer,
someone who wants to use Yosses doesn't have
to go, like, learn how to write TCL for Yosses,
how to load their design and everything.
All they do is literally, like, put down the name
of their design and, you know, Hammer does the rest.
It, like, sets everything up.
It's, like, name, I don't know, a clock period,
like, that's basically all the configuration
that you need.
Yeah, but exactly, like, you could use Yosses
or if you have commercial tools, like, Cadence,
Genus is what we use.
But yeah, so it's definitely, it's not the EDA tool itself,
which makes it, like, very, it makes it much simpler.
I will say the EDA tools are much more complex
than just, like, a VLSI flow tool.
Q: I know, yeah.
I think I had a chance to work with Yosses
a little bit in my undergrads, but yeah.
Yeah, I could understand the complexity.
Yeah, so then I guess you now have the good grasp
on knowledge of the these tools, right?
So what's your next step or, like, I guess,
is this, like, your philosophy with chip design research?
A: Yeah, it's kind of, like, two directions
because I do enjoy the infrastructure
and I think we'll keep just, like,
taping out interesting architectures.
I think on, like, supporting open source tools,
we're thinking of doing, like, introducing, like,
a design space exploration API into Hammer.
Yeah, so basically, like, sort of defining, like,
a flow graph of basically a bunch of iterations,
what variables you want to loop through.
I think that would just improve, like,
the quality of our designs.
We've even thought about, like,
for different steps of the VLSI flow,
like, floor planning or routing or whatever,
like, switching out commercial versus open source tools
and seeing, like, what combination actually works best
because I have a theory.
I have this feeling that, like, you know,
maybe open road is better at placement, say,
but then InnoVis is better at routing.
That's just an example.
So it would be interesting to see, like,
where the open source tools lag
and I have a feeling it's not in everything.
For example, for synthesis, like,
synthesis is so fast and it does a great job.
I feel like synthesis, you don't need a lot.
You just need, like, a mapped net list.
So I think that's interesting.
And then on, like, the research side,
I'm working on, like, power modeling
and developing, like, an RTL power model.
So, like, just having Hammer be able to, like,
easily generate a bunch of, like,
ground truth power numbers has just been super nice.
It was, like, very fast to set up
and I didn't have to know very much about running the tools.
So it's made my research a lot easier, basically.
Q: So, yeah, so, like, with power modeling,
yeah, I guess, what would be your insights?
Or, like, you wanna, like, profile the, like,
I guess, estimate how much power it will take,
like, when you will be using Hammer,
or, like, you wanna build particularly, like,
power-efficient chips, or, like,
what would be your take on that?
A: It's kind of unknown right now.
I think both, like, high-level modeling,
so having just a model that can transfer to new RTL
without having to be retrained
to just get, like, a rough average power estimate,
I think that's one approach.
Just at the architecture level, saying, like,
for these minor RTL changes,
what would the power delta be for a particular workload?
So that's on one side, that's more, like, ML,
learning, like, a good embedding for your RTL.
But then, yeah, on the other side,
and work has already been done in this,
but I think just, first of all, like,
and I'm kind of working on this now,
verifying the state-of-the-art in this,
yeah, like a per-cycle power model
for an RTL running a workload,
and seeing how accurately we can predict,
like, the per-cycle power,
because then you could use it for, yeah,
like, low-power techniques like voltage boosting
and stuff like that.
We have thought about,
I don't think we would implement, like,
some kind of power-saving techniques in a chip,
mainly because it's so difficult to do,
and I think in industry, like,
they have a lot of people to do it,
in academia, that would be very difficult,
but we were talking about
at least implementing some kind of, like,
trying to tape out some kind of power monitors
on a chip to then correlate, like,
what are the power spikes that we're seeing
in, like, physical silicon
versus what we see in simulation.
That was definitely an idea,
but, yeah, still very open-ended,
but basically just trying to gain more insights
earlier in the design cycle
about, like, the power consumption.
Q: So, how do you think the connection
between sustainability, by the way?
So, I think there are, like, a lot of works,
and so, like, in Asplos, I saw
a researcher from U of T,
and she was telling that,
oh, you know, the problem with us
is that we cannot kind of disable
or enable the power or clock stuff
automatically, and this, like,
dynamic voltage schedule,
how is it, like, technology called?
A: DVFS.
Q: Yeah, yeah, yeah, like, and that, like,
it is too energy-consuming because it kind of,
like, it doesn't do it gradually,
it does abruptly and so on, so, like,
I guess your work might be
so cool, integrated or be useful
in that domain, too, right?
A: Yeah, maybe.
That would be interesting because right now,
I still think, yeah, DVFS
can be improved significantly.
Yeah, I'm still
not sure what that would be.
I mean, yeah, it's really difficult
to do on a chip.
Like, I've heard of tape-outs where,
like, the power is much higher than they expected
because they just couldn't turn off modules.
Like, they said they could, and in simulation,
like, maybe it kind of worked,
but then they just weren't able to turn it off,
so it's like they technically had the power gating,
they just didn't gate the module.
So, yeah, I feel like,
yeah, if you're, like, I feel like
at the data center level is where, like,
the power savings would really be.
We were thinking about doing some power modeling
for, like, chiplet-based designs
because then, yeah, exactly, like,
you can design to kind of optimize
the power and, again, yeah,
for some of the, like, higher power cores.
But, yeah, the, yeah,
sustainability part is very difficult
because I feel like Google, for example,
like, they're always like,
oh, we're researching sustainability,
we want lower power, but I'm like,
okay, you're just trying to cut costs
for your data center.
So, it's kind of nice that it goes hand in hand,
but, yeah, I mean,
I guess just making chips in general
is not sustainable,
which is very unfortunate.
Q: Yeah, but, and it's also, I guess,
exciting problem to solve, but, yeah.
So, yeah, I had a question.
So, like, there is, like, a lot of, like,
research because we want to, like,
you want to guys cut the, like,
chip design process, right?
But I heard that, like,
over the two years that usually
is being spent, it's one and a half years
is the time when you go and wait
from the chip designers,
I mean, people who tape out.
Am I right with that?
Or is it, how is the distribution
of the chip design process
and what are you guys particularly
trying to cut off?
Because if it's only about architecture parts
and tape out is too long,
is there anything to resolve on that?
Yeah, I guess I have this.
A: Oh, you say, like, the breakdown
between architectural design
or, like, the physical design?
Q: What is the bottleneck, I guess?
A: See, I'm not really sure.
I feel like every company
does it differently
because, like, in our lab
we have more of, like, an agile flow.
Yeah, because, like, we have RTL generators
and, like, this VLSI flow is very, like,
sort of, I guess it just, like, runs very easily.
So basically, like, as we're doing tape outs
we're both, like, modifying the RTL
and running the backend already.
Which I think companies,
it's a bit more like waterfall.
Like, the RTL architecture gets handed down
and then the RTL designers do it
and then they take a while
and the synthesis takes a while
and then they do handoff to, like, PNR.
So I guess that's what Hammer tried to address
but I think all of these VLSI flow tools do that.
But, yeah, as far as, like, long design time
or I guess, yeah, I'm not quite sure
what, like, the biggest bottleneck is
but, I mean, definitely chip design in general
is just getting more and more costly.
Q: Yeah, I guess also there are a lot of people, clients
and there is only one TSMC, right?
A: Yeah,
Definitely the fabs as well.
We get our chips back at a very, very different rates
depending on where we manufacture them.
Intel has been very fast lately, actually, for us.
Q: Yeah, so I guess one of the last questions would be
so, like, you mentioned these, like,
chip tape-out classes at Berkeley, right?
So how does it go with, like, the structure of the classes?
What do you guys do?
A: Yeah, kind of lack of structure
but, yeah, basically.
Q: Just the fact that you guys tape out the chip is cool.
A: Yeah, it is.
And I think it is enabled by kind of the infrastructure
that we have set up.
It'll get you a chip
even because, like, all the RTL is mostly already there.
But basically, I guess the initial goal of the class
was to tape out a kind of a very lightweight, like,
Bluetooth and CPU sort of meant to be, like,
a little microcontroller,
like a mixed signal chip.
And so on the digital side, we use, like, ChipYard
to just easily generate the RISC-V core and, like, verify it.
And then on the analog end, there's some analog students
that just, like, hand lay out all the analog components,
like the radio and stuff.
So that was, when I did it, that's what it was.
It was, like, 20 students, so about 50-50 analog-digital.
And then everyone had their own task.
So I guess the pros of that is you get to come out
with, like, a very complex chip.
Because I, for example, like, only focused on
the, like, digital compute part.
So only the, like, digital SOC verifying that, whatever.
But there were other people, for example,
who only focused on, like, the digital basebands,
like the interface between the CPU and, like, the radio.
So, I mean, the downside was that, like,
you don't learn about how to make the entire chip.
You only focus on your part.
But as a result, they're able to, like,
make these pretty complex SOCs.
I know some schools, they'll, like, have each student
or, like, pairs of students just work on one block.
And then they'll just put, like, tile all the blocks
on a big, on, like, the chip.
And so you only worked on, like, say,
your little, like, ALU or whatever the thing is.
So that's kind of how it works at Berkeley.
And basically, like, the lectures are kind of
meant to guide you about, like,
what you should be aware of as a chip designer,
like, you know, clock stuff,
just, like, the flow in general,
and a bit of analog design.
But, yeah, it is kind of very freeform, like, whatever.
So, like, last year, they taped up two chips.
That's when Jerry was the TA.
So I guess he, like, talked about that today.
So I think they're trying to scale up the class.
But it could use, like, more structure, for sure.
Q: How many chips you said?
A: Last semester, it was two.
Q: Oh, wow.
So, like, did you guys wait?
How much time did you guys wait?
Like, was it during the semester, or?
A: Yeah, so, okay, my semester was spring 21,
and we did one chip.
And then we got it back.
So we sent it out, like, May.
And then we got it back November, I think.
Not too bad.
Oh, and then last year was the same thing.
So they sent two chips.
My year was TSMC.
Last year was Intel.
They also sent them out, like, May, June,
and got them back, like, November.
So it was, like, a pretty good turnaround.
And basically, like, we have the tape-out class in the spring.
And then in the fall, we have, like, a chip bring-up class,
where we, like, kind of teach the students, like,
how to test these chips.
That one is even less structured.
We're kind of trying to work on, like, a better bring-up flow for the chips.
But the idea is to, like, get a cycle going of, like,
some students tape out, and then a subset of those students
take the bring-up class, so they get to bring up their chip.
But also, like, a set of new students come in,
bring up someone else's chip.
And then hopefully some of those students who brought up someone else's chip
then go and, like, tape out their own chip.
So it's kind of like you're supposed to kind of learn.
So I think it kind of worked.
I think from bringing up the chip,
they learned, like, some of the pitfalls.
So I think they're doing better this semester.
But, yeah, they're definitely pretty complex
and definitely very difficult to do for undergrads.
But I think they're kind of doing their best.
Q: Wow, that's definitely cool.
It sounds very fun.
I guess it's time to wrap up, but I can ask one final question,
which is what is your, I guess, you can choose between.
What is your wisdom for early-stage PhD students or maybe to undergrads?
Or what's your favorite open-source license?
A: Well, I don't know too much about licenses.
Then, cool, I'll do my wisdom.
Yeah, I guess I would say focus on, like, learning the fundamentals
as opposed to, you know, trying to publish
or trying to, like, have your own project or something.
I feel like don't put pressure on yourself
to, like, produce really high-quality work like your first year
or even an undergrad.
Like, yeah, just focus on, like, learning as much as you can
because you'll just be much stronger when you actually start working on stuff.
I feel like I know people, like, we started the same year,
but they focused, I think, too much on research their first couple years.
And now I just feel like they really, like, don't understand, like, VLSI very well
or, like, they don't understand it very deeply
because they didn't bother, like, taping out a chip just to learn about it.
They were just trying to do their research project right from the beginning.
So I think just, like, kind of chill out and, like, you know,
make friends in lab, make friends with the older students, just, like, learn a lot.
Yeah, go to LATCHUP.
Q: Oh, yeah, definitely.
Yeah, I think it is – yeah, sometimes people get very, I guess, ambitious
and try to, like, start with the papers or come up with some, like, very –
there will be some papers that are hard to come up with
and then in that time you lose some opportunities of learning fundamentals.
A: Exactly, yeah.
I think one of the good advice was, like, from Krzysztof Osanowicz
because he was, like – he taught computer architecture when I took it
and he just really emphasized, like, learning the history of computer architecture.
So he would take us back and, like, tell us about, you know,
machines that were being built in the 70s and 80s.
Like, the first vector machine and all these different things.
And it kind of makes you realize, like, wow, like, no idea is new.
It's just about, like, the timing of it.
Like, you know, it's like the – whatever, the Perceptron came out in, like, the 50s,
but ML only blew up, like, 10 years ago because, like, that's when compute actually caught up.
So it's like ML is nothing new.
It's just compute was, like, actually caught up enough to make it, like, feasible.
So, yeah, I feel like it kind of makes you feel better.
It's like you don't have to have a groundbreaking idea.
Like, sometimes – yeah, it's like basically everything that could have been thought of
has already been thought of already.
It's just about, like, I guess the timing of it and being smart
and having the intuition to know, like, what's going to work or probably will work.
Q: Got it, I gues it is time to wrap up! Thanks for your time!